Method and apparatus for sensing environment using a wireless passive sensor

ABSTRACT

A method for execution by a RFID tag includes receiving, by an antenna of the RFID tag, an RF signal from an RFID reader, where the RF signal has a carrier frequency. The method further includes determining, by a tuning circuit of the RFID tag, a received power level of the RF signal at the carrier frequency and whether the received power level compares favorably to a power level threshold. When the received power level compares unfavorably to the power level threshold, the method further includes adjusting, by the tuning circuit, the input impedance of the RFID tag by adjusting a tank circuit of the RFID tag until the received power level compares favorably to the power level threshold, where the input impedance of the RFID tag is based on one or more of impedance of the antenna and impedance of the tank circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present U.S. Utility Patent Application claims priority pursuant to 35 U.S.C. § 120 as a Continuation-In-Part of U.S. Utility application Ser. No. 15/665,046, entitled “METHOD AND APPARATUS FOR SENSING ENVIRONMENT USING A WIRELESS PASSIVE SENSOR”, filed 31 Jul. 2017, which claims priority pursuant to 35 U.S.C. § 120 as a Continuation of U.S. Utility application Ser. No. 14/256,877, entitled “METHOD AND APPARATUS FOR SENSING ENVIRONMENT USING A WIRELESS PASSIVE SENSOR”, filed 18 Apr. 2014, now U.S. Pat. No. 9,785,807 issued on 10 Oct. 2017, which is incorporated herein by reference in its entirety and made part of the present U.S. Utility Patent Application for all purposes, and said Ser. No. 14/256,877 is a Continuation-In-Part of application Ser. No. 13/209,420, filed 14 Aug. 2011 (“Parent Application One”), now U.S. Pat. No. 8,749,319, issued on 10 Jun. 2014, which claims priority to U.S. Provisional Application Ser. No. 61/428,170, filed 29 Dec. 2010 (“Parent Provisional One”) and U.S. Provisional Application Ser. No. 61/485,732, filed 13 May 2011 (“Parent Provisional Two”). Parent Application One (Ser. No. 13/209,420) is, in turn, a Continuation-In-Part of application Ser. No. 12/462,331, filed 1 Aug. 2009, which is now U.S. Pat. No. 8,081,043, issued 20 Dec. 2011 (“Parent Patent One”), which is a Divisional of U.S. Utility application Ser. No. 11/601,085, filed 18 Nov. 2006, now U.S. Pat. No. 7,586,385, issued on 8 Sep. 2009.

U.S. Utility application Ser. No. 14/256,877 is also a Continuation-In-Part of application Ser. No. 13/467,925, filed 9 May 2012 (“Parent Application Two”), which is a Continuation-in-Part of U.S. Utility application Ser. No. 13/209,425, filed 14 Aug. 2011, now U.S. Pat. No. 9,048,819, issued on 2 Jun. 2015, which claims priority pursuant to 35 U.S.C. § 119(e) to U.S. Provisional Application No. 61/428,170, filed 29 Dec. 2010 and U.S. Provisional Application No. 61/485,732, filed 13 May 2011, and U.S. Utility application Ser. No. 13/209,425 also claims priority pursuant to 35 U.S.C. § 120 as a Continuation-in-Part of U.S. Utility application Ser. No. 12/462,331, filed 1 Aug. 2009, now U.S. Pat. No. 8,081,043, issued on 20 Dec. 2011, which is a Divisional of U.S. Utility application Ser. No. 11/601,085, filed 18 Nov. 2006, now U.S. Pat. No. 7,586,385, issued on 8 Sep. 2009.

U.S. Utility application Ser. No. 14/256,877 is also a Continuation-In-Part of application Ser. No. 13/209,425, filed simultaneously with the Parent Application One on 14 Aug. 2011 (“Related Co-application”), now U.S. Pat. No. 9,048,819, issued on 2 Jun. 2015, which claims priority pursuant to 35 U.S.C. § 119(e) to U.S. Provisional Application No. 61/428,170, filed 29 Dec. 2010 and U.S. Provisional Application No. 61/485,732, filed 13 May 2011, and U.S. Utility application Ser. No. 13/209,425 also claims priority pursuant to 35 U.S.C. § 120 as a Continuation-in-Part of U.S. Utility application Ser. No. 12/462,331, filed 1 Aug. 2009, now U.S. Pat. No. 8,081,043, issued on 20 Dec. 2011, which is a Divisional of U.S. Utility application Ser. No. 11/601,085, filed 18 Nov. 2006, now U.S. Pat. No. 7,586,385, issued on 8 Sep. 2009.

U.S. Utility application Ser. No. 14/256,877 also claims priority to:

1. U.S. Provisional Application Ser. No. 61/814,241, filed 20 Apr. 2013, (“Parent Provisional Three”);

2. U.S. Provisional Application Ser. No. 61/833,150, filed 10 Jun. 2013, (“Parent Provisional Four”);

3. U.S. Provisional Application Ser. No. 61/833,167, filed 10 Jun. 2013, (“Parent Provisional Five”);

4. U.S. Provisional Application Ser. No. 61/833,265, filed 10 Jun. 2013, (“Parent Provisional Six”);

5. U.S. Provisional Application Ser. No. 61/871,167, filed 28 Aug. 2013, (“Parent Provisional Seven”);

6. U.S. Provisional Application Ser. No. 61/875,599, filed 9 Sep. 2013, (“Parent Provisional Eight”);

7. U.S. Provisional Application Ser. No. 61/896,102, filed 27 Oct. 2013, (“Parent Provisional Nine”);

8. U.S. Provisional Application Ser. No. 61/929,017, filed 18 Jan. 2014, (“Parent Provisional Ten”);

9. U.S. Provisional Application Ser. No. 61/934,935, filed 3 Feb. 2014, (“Parent Provisional Eleven”);

collectively, “Parent Provisional References”, and hereby claims benefit of the filing dates thereof pursuant to 37 CFR § 1.78(a)(4).

The subject matter of the Parent Applications One, Two and Three, Parent Patent One, the Related Co-application, and the Parent Provisional References (collectively, “Related References”), each in its entirety, is expressly incorporated herein by reference.

BACKGROUND OF THE INVENTION Technical Field of the Invention

The present invention relates generally to sensing a detectable environmental condition, and, in particular, to sensing a detectable environmental condition in a passive RFID system.

Description of Related Art

In general, in the descriptions that follow, we will italicize the first occurrence of each special term of art that should be familiar to those skilled in the art of radio frequency (“RF”) communication systems. In addition, when we first introduce a term that we believe to be new or that we will use in a context that we believe to be new, we will bold the term and provide the definition that we intend to apply to that term. In addition, throughout this description, we will sometimes use the terms assert and negate when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, we may refer to the mutually exclusive boolean states as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.

In accordance with our prior invention previously disclosed in the Related References, the amplitude modulated (“AM”) signal broadcast by the reader in an RFID system will be electromagnetically coupled to a conventional antenna, and a portion of the current induced in a tank circuit is extracted by a regulator to provide operating power for all other circuits. Once sufficient stable power is available, the regulator will produce, e.g., a power-on-reset signal to initiate system operation. Thereafter, the method disclosed in the Related References, and the associated apparatus, dynamically varies the capacitance of a variable capacitor component of the tank circuit so as to dynamically shift the f_(R) of the tank circuit to better match the f_(C) of the received RF signal, thus obtaining maximum power transfer in the system.

In general, the invention disclosed in the Related References focused primarily on quantizing the voltage developed by the tank circuit as the primary means of matching the f_(R) of the tank circuit to the transmission frequency, f_(C), of the received signal. However, this voltage quantization is, at best, indirectly related to received signal field strength. In the First Related Application, we disclosed an effective and efficient method and apparatus for quantizing the received field strength as a function of induced current. In particular, we disclosed a method and apparatus adapted to develop this field quantization in a form and manner that is suitable for selectively varying the input impedance of the receiver circuit to maximize received power, especially during normal system operation. Additionally, in light of the power sensitive nature of RFID systems, our disclosed method and apparatus varied the input impedance with a minimum power loss.

In Parent Application One, we have disclosed generally the use of our method and apparatus to sense changes to an environment to which the RFID tag is exposed. In this application, we will further develop this capability and disclose embodiments specifically adapted to operate in a variety of environments.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 illustrates, in block diagram form, an RF receiver circuit having a field strength detector constructed in accordance with an embodiment of our invention;

FIG. 2 illustrates, in block diagram form, a field strength detector circuit constructed in accordance with an embodiment of our invention;

FIG. 3 illustrates, in block schematic form, a more detailed embodiment of the field strength detector circuit shown in FIG. 2;

FIG. 4 illustrates, in flow diagram form, the sequencing of operations in the field strength detector circuit shown in FIG. 3;

FIG. 5 illustrates, in graph form, the response of the field strength detector circuit shown in FIG. 3 to various conditions;

FIG. 6 illustrates, in block schematic form, an RF receiver circuit constructed in accordance with another embodiment of our invention;

FIG. 7 illustrates, in flow diagram form, the sequencing of the operations in the RF receiver circuit shown in FIG. 6;

FIG. 8 illustrates, in block schematic form, an alternative representation of the impedance represented by the antenna and the tank circuit of the exemplary RFID receiver circuit;

FIG. 9 illustrates, in block schematic form, an alternative exemplary embodiment of the field strength detector circuit shown in FIG. 3;

FIG. 10 illustrates, in block schematic form, an alternative exemplary embodiment of the field strength detector circuit shown in FIG. 3;

FIG. 11 illustrates, in block schematic form, an exemplary RFID sub-system containing tag and reader;

FIG. 12 illustrates, in flow diagram form, the sequencing of the operations in developing a reference table associating tank tuning parameters with system frequency;

FIG. 13, comprising FIGS. 13a and 13b , illustrates an RF system constructed in accordance with one embodiment of our invention to sense environmental conditions in a selected region surrounding the system;

FIG. 14 illustrates, in perspective, exploded view, one possible configuration of an antenna and tail arrangement adapted for use in the system of FIG. 13;

FIG. 15, comprising FIG. 15a through FIG. 15h , illustrates an antenna constructed in accordance with one embodiment of the present invention, wherein: FIG. 15a illustrates in top plan view a fully assembled antenna; FIG. 15b and FIG. 15c illustrate, in cross-section, the several layers comprising a head and a tail portion, respectively, of the antenna; FIG. 15d through FIG. 15g illustrate, in plan view, the several separate layers of the antenna as shown in FIG. 15b and FIG. 15c ; and FIG. 15h illustrates, in partial plan view, a close-up depiction of a central, slot portion of the antenna of FIG. 15a (as noted in FIG. 15e ) showing in greater detail the construction of antenna elements to which an RFID tag die may be attached;

FIG. 16 illustrates, in flow diagram form, the sequencing of the operations in detecting the presence of a contaminant using, e.g., the antenna of FIG. 15 in the system shown in FIG. 11;

FIG. 17, comprising FIG. 17a and FIG. 17b , illustrates a folded, patch antenna constructed in accordance with one other embodiment of the present invention, wherein: FIG. 17a illustrates, in plan view, the top layer of the antenna after placement of the RFID tag die but before folding along fold lines 1 and 2; and FIG. 17b illustrates, also in plan view, the bottom layer of the antenna as shown in FIG. 17a ; and

FIG. 18 is a logic diagram of an example of a method of adjusting impedance of a radio frequency identification (RFID) tag in accordance with a power level threshold in accordance with the present invention.

In the drawings, similar elements will be similarly numbered whenever possible. However, this practice is simply for convenience of reference and to avoid unnecessary proliferation of numbers and is not intended to imply or suggest that our invention requires identity in either function or structure in the several embodiments.

DETAILED DESCRIPTION OF THE INVENTION

Shown in FIG. 1 is an RF receiver circuit 10 suitable for use in an RFID application. As we have described in our Related References, an RF signal electromagnetically coupled to an antenna 12 is received via a tank circuit 14, the response frequency, f_(R), of which is dynamically varied by a tuner 16 to better match the transmission frequency, f_(C), of the received RF signal, thus obtaining a maximum power transfer. In particular, as further noted in the Related Applications, the RMS voltage induced across the tank circuit 14 by the received RF signal is quantized by tuner 16 and the developed quantization employed to control the impedance of the tank circuit 14. As also described in the Related References, the unregulated, AC current induced in the tank circuit 14 by the received RF signal is conditioned by a regulator 18 to provide regulated DC operating power to the receiver circuit 10. In accordance with our present invention, we now provide a field strength detector 20, also known as a power detector, adapted to develop a field-strength value as a function of the field strength of the received RF signal. As we have indicated in FIG. 1, our field strength detector 20 is adapted to cooperate with the regulator 18 in the development of the field-strength value. As we shall disclose below, if desired, our field strength detector 20 can be adapted to cooperate with the tuner 16 in controlling the operating characteristics of the tank circuit 14.

Shown by way of example in FIG. 2 is one possible embodiment of our field strength or power detector 20. In this embodiment, we have chosen to employ a shunt-type regulator 18 so that, during normal operation, we can use the shunted ‘excess’ current as a reference against which we develop the field-strength value. In this regard, we use a reference 22 first to develop a shunt current reference value proportional to the shunted current, and then to develop a mirrored current reference value as a function of both the shunted current and a field strength reference current provided by a digitally-controlled current source 24. Preferably, once the tuner 16 has completed its initial operating sequence, whereby the f_(R) of the tank circuit 14 has been substantially matched to the f_(C) of the received signal, we then enable a digital control 26 to initiate operation of the current source 24 at a predetermined, digitally-established minimum field strength reference current. After a predetermined period of time, control 26 captures the mirrored current reference value provided by the current reference 22, compares the captured signal against a predetermined threshold value, and, if the comparison indicates that the field strength reference current is insufficient, increases, in accordance with a predetermined sequence of digital-controlled increments, the field strength reference current; upon the comparison indicating that the field strength reference current is sufficient, control 26 will, at least temporarily, cease operation.

In accordance with our invention, the digital field-strength value developed by control 26 to control the field strength current source 24 is a function of the current induced in the tank circuit 14 by the received RF signal. Once developed, this digital field-strength value can be employed in various ways. For example, it can be selectively transmitted by the RFID device (using conventional means) back to the reader (not shown) for reference purposes. Such a transaction can be either on-demand or periodic depending on system requirements. Imagine for a moment an application wherein a plurality of RFID tag devices are distributed, perhaps randomly, throughout a restricted, 3-dimensional space, e.g., a loaded pallet. Imagine also that the reader is programmed to query, at an initial field strength, all tags “in bulk” and to command all tags that have developed a field-strength value greater than a respective field-strength value to remain ‘silent.’ By performing a sequence of such operations, each at an increasing field strength, the reader will, ultimately, be able to isolate and distinguish those tags most deeply embedded within the space; once these ‘core’ tags have been read, a reverse sequence can be performed to isolate and distinguish all tags within respective, concentric ‘shells’ comprising the space of interest. Although, in all likelihood, these shells will not be regular in either shape or relative volume, the analogy should still be apt.

In FIG. 3, we have illustrated one possible embodiment of our field strength detector 20 a. In general, we have chosen to use a shunt circuit 18 a to develop a substantially constant operating voltage level across supply node 28 and ground node 30. Shunt regulators of this type are well known in the art, and typically use zener diodes, avalanche breakdown diodes, diode-connected MOS devices, and the like.

As can be seen, we have chosen to implement current reference 22 in the form of a current mirror circuit 22 a, connected in series with shunt circuit 18 a between nodes 28 and 30. As is typical, current mirror circuit 22 a comprises a diode-connected reference transistor 32 and a mirror transistor 34. If desired, a more sophisticated circuit such as a Widlar current source may be used rather than this basic two-transistor configuration. For convenience of reference, we have designated the current shunted by shunt circuit 18 a via reference transistor 32 as i_(R); similarly, we have designated the current flowing through mirror transistor 34 as i_(R)/N, wherein, as is known, N is the ratio of the widths of reference transistor 32 and mirror transistor 34.

We have chosen to implement the field strength current source 24 as a set of n individual current sources 24 a, each connected in parallel between the supply node 28 and the mirror transistor 34. In general, field strength current source 24 a is adapted to source current at a level corresponding to an n-bit digital control value developed by a counter 38. In the illustrated embodiment wherein n=5, field strength current source 24 a is potentially capable of sourcing thirty-two distinct reference current levels. We propose that the initial, minimum reference current level be selected so as to be less than the current carrying capacity of the mirror transistor 34 when the shunt circuit 18 a first begins to shunt excess induced current through reference transistor 32; that the maximum reference current level be selected so as to be greater than the current carrying capacity of the mirror transistor 34 when the shunt circuit 18 a is shunting a maximum anticipated amount of excess induced current; and that the intermediate reference current levels be distributed relatively evenly between the minimum and maximum levels. Of course, alternate schemes may be practicable, and, perhaps, desirable depending on system requirements.

Within control 26 a, a conventional analog-to-digital converter (“ADC”) 40, having its input connected to a sensing node 36, provides a digital output indicative of the field strength reference voltage, v_(R), developed on sensing node 36. In one embodiment, ADC 40 may comprise a comparator circuit adapted to switch from a logic_0 state to a logic_1 when sufficient current is sourced by field strength current source 24 a to raise the voltage on sensing node 36 above a predetermined reference voltage threshold, v_(th). Alternatively, ADC 40 may be implemented as a multi-bit ADC capable of providing higher precision regarding the specific voltage developed on sensing node 36, depending on the requirements of the system. Sufficient current may be characterized as that current sourced by the field strength current source 24 a or sunk by mirror transistor 34 such that the voltage on sensing node 36 is altered substantially above or below a predetermined reference voltage threshold, v_(th). In the exemplary case of a simple CMOS inverter, v_(th) is, in its simplest form, one-half of the supply voltage (VDD/2). Those skilled in the art will appreciate that v_(th) may by appropriately modified by altering the widths and lengths of the devices of which the inverter is comprised. In the exemplary case a multi-bit ADC, v_(th) may be established by design depending on the system requirements and furthermore, may be programmable by the system.

In the illustrated embodiment, a latch 42 captures the output state of ADC 40 in response to control signals provided by a clock/control circuit 44. If the captured state is logic_0, the clock/control circuit 44 will change counter 38 to change the reference current being sourced by field strength current source 24 a; otherwise clock/control circuit 44 will, at least temporarily, cease operation. However, notwithstanding, the digital field-strength value developed by counter 38 is available for any appropriate use, as discussed above.

By way of example, we have illustrated in FIG. 4 one possible general operational flow of our field strength detector 20 a. Upon activation, counter 38 is set to its initial digital field-strength value (step 48), thereby enabling field strength current source 24 a to initiate reference current sourcing at the selected level. After an appropriate settling time, the field strength reference voltage, v_(R), developed on sensing node 36 and digitized by ADC 40 is captured in latch 42 (step 50). If the captured field strength reference voltage, v_(R), is less than (or equal to) the predetermined reference threshold voltage, v_(th), clock/control 44 will change counter 38 (step 54). This process will repeat, changing the reference current sourced by field strength current source 24 a until the captured field strength reference voltage, v_(R), is greater than the predetermined reference threshold voltage, v_(th), (at step 52), at which time the process will stop (step 56). As illustrated, this sweep process can be selectively reactivated as required, beginning each time at either the initial field-strength value or some other selected value within the possible range of values as desired.

The graph illustrated in FIG. 5 depicts several plots of the voltage developed on sensing node 36 as the field strength detector circuit 20 a sweeps the value of counter 38 according to the flow illustrated in FIG. 4. As an example, note that the curve labeled “A” in FIG. 5 begins at a logic_0 value when the value of counter 38 is at a minimum value such as “1” as an exemplary value. Subsequent loops though the sweep loop gradually increase the field strength reference voltage on sensing node 36 until counter 38 reaches a value of “4” as an example. At this point, the “A” plot in FIG. 5 switches from a logic_0 value to a logic_1 value, indicating that the field strength reference voltage, v_(R), on sensing node 36 has exceeded the predetermined reference threshold voltage, v_(th). Other curves labeled “B” through “D” depict incremental increases of reference currents, i_(R), flowing through reference device 32, resulting in correspondingly higher mirrored currents flowing through mirror device 34. This incrementally higher mirror current requires field strength current source 24 to source a higher current level which in turn corresponds to higher values in counter 38. Thus, it is clear that our invention is adapted to effectively and efficiently develop a digital representation of the current flowing through sensing node 36 that is suitable for any appropriate use.

One such use, as discussed earlier, of our field strength detector 20 is to cooperate with tuner 16 in controlling the operating characteristics of the tank circuit 14. FIG. 6 illustrates one possible embodiment where receiver circuit 10 a uses a field strength detector 20 b specially adapted to share with tuner 16 a the control of the tank circuit 14. In our Related References we have disclosed methods, and related apparatus, for dynamically tuning, via tuner 16 a, the tank circuit 14 so as to dynamically shift the f_(R) of the tank circuit 14 to better match the f_(C) of the received RF signal at antenna 12. By way of example, we have shown in FIG. 6 how the embodiment shown in FIG. 3 of our Parent Patent may be easily modified by adding to tuner 16 a a multiplexer 58 to facilitate shared access to the tuner control apparatus. Shown in FIG. 7 is the operational flow (similar to that illustrated in FIG. 4 in our Parent Patent) of our new field strength detector 20 b upon assuming control of tank circuit 14.

In context of this particular use, once tuner 16 a has completed its initial operating sequences as fully described in our Parent Patent, and our field strength detector 20 b has performed an initial sweep (as described above and illustrated in FIG. 4) and saved in a differentiator 60 a base-line field-strength value developed in counter 38, clock/control 44 commands multiplexer 58 to transfer control of the tank circuit 16 a to field strength detector 20 b (all comprising step 62 in FIG. 7). Upon completing a second current sweep, differentiator 60 will save the then-current field-strength value developed in the counter 38 (step 64). Thereafter, differentiator 60 will determine the polarity of the change of the previously saved field-strength value with respect to the then-current field-strength value developed in counter 38 (step 66). If the polarity is negative (step 68), indicating that the current field-strength value is lower than the previously-saved field-strength value, differentiator 60 will assert a change direction signal; otherwise, differentiator 60 will negate the change direction signal (step 70). In response, the shared components in tuner 16 a downstream of the multiplexer 58 will change the tuning characteristics of tank circuit 14 (step 72) (as fully described in our Related References). Now, looping back (to step 64), the resulting change of field strength, as quantized is the digital field-strength value developed in counter 38 during the next sweep (step 64), will be detected and, if higher, will result in a further shift in the f_(R) of the tank circuit 14 in the selected direction or, if lower, will result in a change of direction (step 70). Accordingly, over a number of such ‘seek’ cycles, our invention will selectively allow the receiver 10 a to maximize received field strength even if, as a result of unusual factors, the f_(R) of the tank circuit 14 may not be precisely matched to the f_(C) of the received RF signal, i.e., the reactance of the antenna is closely matched with the reactance of the tank circuit, thus achieving maximum power transfer. In an alternative embodiment, it would be unnecessary for tuner 16 a to perform an initial operating sequence as fully described in our Parent Patent. Rather, field strength detector 20 b may be used exclusively to perform both the initial tuning of the receiver circuit 10 a as well as the subsequent field strength detection. Note that the source impedance of antenna 12 and load impedance of tank circuit 14 may be represented alternatively in schematic form as in FIG. 8, wherein antenna 12 is represented as equivalent source resistance R_(S) 74 and equivalent source reactance Xs 76, and tank circuit 14 is represented as equivalent load resistance R_(L) 78 and equivalent, variable load reactance XL 80.

In FIG. 9, we have illustrated alternate embodiments of our field strength detector illustrated in FIG. 3. Here, as before, shunt circuit 18 b is used to develop a substantially constant operating voltage level across supply node 28 and ground node 30. Also as before, the current reference 22 is implemented as a current mirror circuit 22 b connected in series with shunt circuit 18 b between nodes 28 and 30. However, in this embodiment, the field strength current source comprises a resistive component 84 adapted to function as a static resistive pull-up device. Many possible implementations exist besides a basic resistor, such as a long channel length transistor, and those skilled in the art will appreciate the various implementations that are available to accomplish analogous functionality. The field strength voltage reference v_(R) developed on sensing node 36 will be drawn to a state near the supply voltage when the mirrored current flowing though transistor 34 is relatively small, e.g. close to zero amps, indicating a weak field strength. As the field strength increases, the current flowing through mirror transistor 34 will increase, and the field strength voltage reference v_(R) developed on sensing node 36 will drop proportionally to the mirrored current flowing through mirror transistor 34 as ix/N. ADC 40, having its input connected to sensing node 36, provides a digital output indicative of the field strength reference voltage, v_(R), developed on sensing node 36, as described previously.

In this alternate embodiment, latch 42 captures the output state of ADC 40 in response to control signals provided by a clock/control circuit 44. As disclosed earlier, the ADC 40 may comprise a comparator circuit. In this instance, ADC 40 is adapted to switch from a logic_1 state to a logic_0 when sufficient current is sunk by mirror transistor 34 to lower the voltage on sensing node 36 below a predetermined reference voltage threshold, v_(th). Alternatively, ADC 40 may be implemented as a multi-bit ADC capable of providing higher precision regarding the specific voltage developed on sensing node 36, depending on the requirements of the system.

Comparator 82 subsequently compares the captured output state held in latch 42 with a value held in counter 38 that is selectively controlled by clock/control circuit 44. In response to the output generated by comparator 82, clock/control circuit 44 may selectively change the value held in counter 38 to be one of a higher value or a lower value, depending on the algorithm employed. Depending upon the implementation of counter 38 and comparator 82, clock/control circuit 44 may also selectively reset the value of counter 38 or comparator 82 or both. The digital field-strength value developed by counter 38 is available for any appropriate use, as discussed above.

In FIG. 10, we have illustrated another alternate embodiment of our field strength detector illustrated in FIG. 3. Here, as before, shunt circuit 18 c is used to develop a substantially constant operating voltage level across supply node 28 and ground node 30. In this embodiment, the current reference 22 is implemented as a resistive component 86 that functions as a static pull-down device. Many possible implementations exist besides a basic resistor, such as a long channel length transistor and those skilled in the art will appreciate the various implementations that are available to accomplish analogous functionality. The field strength voltage reference v_(R) developed on sensing node 36 will be drawn to a state near the ground node when the current flowing though shunt circuit 18 c is relatively small, e.g. close to zero amps, indicating a weak field strength. As the field strength increase, the current flowing through shunt circuit 18 c will increase, and the field strength voltage reference v_(R) developed on sensing node 36 will rise proportionally to the current flowing through shunt circuit 18 c. ADC 40, having its input connected to a sensing node 36, provides a digital output indicative of the field strength reference voltage, v_(R), developed on sensing node 36, as described previously.

In this alternate embodiment, latch 42 captures the output state of ADC 40 in response to control signals provided by a clock/control circuit 44. As disclosed earlier, the ADC 40 may comprise a comparator circuit. In this instance, ADC 40 is adapted to switch from a logic_0 state to a logic_1 when sufficient current is sourced by shunt circuit 18 c to raise the voltage on sensing node 36 above a predetermined reference voltage threshold, v_(th). Alternatively, ADC 40 may be implemented as a multi-bit ADC capable of providing higher precision regarding the specific voltage developed on sensing node 36, depending on the requirements of the system.

Comparator 82 subsequently compares the captured output state held in latch 42 with a value held in counter 38 that is selectively controlled by clock/control circuit 44. In response to the output generated by comparator 82, clock/control circuit 44 may selectively change the value held in counter 38 to be one of a higher value or a lower value, depending on the algorithm employed. Depending upon the implementation of counter 38 and comparator 82, clock/control circuit 44 may also selectively reset the value of counter 38 or comparator 82 or both. The digital field-strength value developed by counter 38 is available for any appropriate use, as discussed above.

In another embodiment, our invention may be adapted to sense the environment to which a tag is exposed, as well as sensing changes to that same environment. As disclosed in our Related References, the auto-tuning capability of tuner 16 acting in conjunction with tank circuit 14 detects antenna impedance changes. These impedance changes may be a function of environmental factors such as proximity to interfering substances, e.g., metals or liquids, as well as a function of a reader or receiver antenna orientation. Likewise, as disclosed herein, our field strength (i.e., received power) detector 20 may be used to detect changes in received power (i.e., field strength) as a function of, for example, power emitted by the reader, distance between tag and reader, physical characteristics of materials or elements in the immediate vicinity of the tag and reader, or the like. Sensing the environment or, at least, changes to the environment is accomplished using one or both of these capabilities.

As an example, the tag 88 of FIG. 11, contains both a source tag antenna 12 (not shown, but see, e.g., FIG. 6) and a corresponding load chip tank circuit 14 (not shown, but see, e.g., FIG. 6). Each contains both resistive and reactive elements as discussed previously (see, e.g., FIG. 8). A tag 88 containing such a tank circuit 14 mounted on a metallic surface will exhibit antenna impedance that is dramatically different than the same tag 88 in free space or mounted on a container of liquid. Shown in Table 1 are exemplary values for impedance variations in both antenna source resistance 74 as well as antenna source reactance 76 as a function of frequency as well as environmental effects at an exemplary frequency.

TABLE 1 Antenna Impedance Variations 860 MHz 870 MHz 880 MHZ 890 MHz Rs, Ω Xs, Ω Rs, Ω Xs, Ω Rs, Ω Xs, Ω Rs, Ω Xs,Ω In Air 1.3 10.7 1.4 10.9 1.5 11.2 1.6 11.5 On Metal 1.4 10.0 1.5 10.3 1.6 10.6 1.7 10.9 On Water 4.9 11.3 1.8 11.1 2.4 11.7 2.9 11.5 On Glass 1.8 11.1 2.0 11.4 2.2 11.7 2.5 12.0 On Acrylic 1.4 10.6 1.6 11.1 1.7 11.4 1.9 11.7 900 MHZ 910 MHZ 920 MHZ 930 MHZ Rs, Ω Xs, Ω Rs, Ω Xs, Ω Rs, Ω Xs,Ω Rs, Ω Xs,Ω In Air 1.8 11.8 2.0 12.1 2.2 12.4 2.4 12.8 On Metal 1.9 11.2 2.1 11.6 2.3 12.0 2.6 12.4 On Water 2.5 12.3 3.0 12.7 5.8 14.1 9.1 13.2 On Glass 2.8 12.4 3.2 12.8 3.7 13.2 4.2 13.6 On Acrylic 2.0 12.1 2.3 12.4 2.5 12.8 2.8 13.2

The tuner circuit 16 of our invention as disclosed in the Related References automatically adjusts the load impendence by adjusting load reactance 80 (see, e.g., FIG. 8) to match source antenna impedance represented by source resistance 74 (see, e.g., FIG. 8) and source reactance 76 (see, e.g., FIG. 8). As previously disclosed, matching of the chip load impedance and antenna source impedance can be performed automatically in order to achieve maximum power transfer between the antenna and the chip. My invention as disclosed in the Related References contained a digital shift register 90 for selectively changing the value of the load reactive component 80 (see, e.g., FIG. 8), in the present case a variable capacitor, until power transfer is maximized. (For reference, digital shift register 90 corresponds to shift register 64 in FIG. 5 of the Parent Patent.) This digital value of the matched impendence may be used either internally by the tag 88, or read and used by the reader 92, to discern relative environmental information to which the tag 88 is exposed. For example, tag 88 may contain a calibrated look-up-table within the clock/control circuit 44 which may be accessed to determine the relevant environmental information. Likewise, a RFID reader 92 may issue commands (see transaction 1 in FIG. 11) to retrieve (see transaction 2 in FIG. 11) the values contained in digital shift register 90 via conventional means, and use that retrieved information to evaluate the environment to which tag 88 is exposed. The evaluation could be as simple as referencing fixed data in memory that has already been stored and calibrated, or as complex as a software application running on the reader or its connected systems for performing interpretive evaluations.

Likewise, consider a tag 88 containing our field strength (i.e., received power) detector 20 (not shown, but, e.g., see FIG. 6) wherein the method of operation of the system containing the tag 88 calls for our field strength detector 20 to selectively perform its sweep function and developing the quantized digital representation of the current via the method discussed earlier. As illustrated in FIG. 11, counter 38 will contain the digital representation developed by our field strength detector 20 of the RF signal induced current, and may be used either internally by the tag 88, or read and used by the reader 92, to discern relative environmental information to which the tag 88 is exposed. For example, reader 92 may issue a command to the tag 88 (see transaction 1 in FIG. 11) to activate tuner 16 and/or detector 20 and, subsequent to the respective operations of tuner 16 and/or detector 20, receive (see transaction 2 in FIG. 11) the digital representations of either the matched impedance or the maximum current developed during those operations. Once again, this digital value of the field strength stored in the counter 38 may be used either internally by the tag 88, or read and used by the reader 92, to discern relative environmental information to which the tag 88 is exposed. For example, tag 88 may contain a calibrated look-up-table within the clock and control block 44 which may be accessed to determine the relevant environmental information. Likewise, a RFID reader may issue commands to retrieve the values contained in digital shift register 90, and use that retrieved information to evaluate the environment to which tag 88 is exposed. The evaluation could be as simple as referencing fixed data in memory that has already been stored and calibrated, or as complex as a software application running on the reader or its connected systems for performing interpretive evaluations. Thus, the combining of the technologies enables a user to sense the environment to which a tag 88 is exposed as well as sense changes to that same environment.

As we have explained in the Parent Provisional One, it is well known that changes in some environmental factors will result in respective changes the effective impedance of the antenna 12. In a number of the Related References, we have shown that it is possible to dynamically retune the tank circuit 14 to compensate for the environmentally-induced change in impedance by systematically changing the digital tuning parameters of tank circuit 14, using techniques disclosed, inter alia, in Parent Patent One. We will now show how it is possible to develop an estimate of the relative change in the environmental factor as a function of the relative change in the digital tuning parameters of the tank circuit 14.

As can be seen in Table 1, above, it is possible to develop, a priori, a reference table storing information relating to a plurality of environmental reference conditions. Thereafter, in carefully controlled conditions wherein one and only one environmental condition of interest is varied (see, FIG. 12), an operational tag 88 is exposed to each of the stored reference conditions (step 94) and allowed to complete the tank tuning process. (recursive steps 96 and 98). After tuning has stabilized, the tag 88 can be interrogated (step 100), and the final value in the shift register 90 retrieved (step 100). This value is then stored in the reference table in association with the respective environmental condition (step 102). The resulting table might look like this:

TABLE 2 Tuning Parameters vs. Frequency 860 870 880 890 900 910 920 930 MHz MHz MHz MHz MHz MHz MHz MHz In Air 25 21 16 12 8 4 0  0* On Metal 31 27 22 17 12 8 3  0  On Water 20 19 12 12 4 0 0* 0* On Glass 21 17 12 8 4  0* 0* 0* On Acrylic 23 19 14 10 6 2 0* 0* 0*indicates that a lower code was needed but not available; 0 is a valid code.

In contrast to prior art systems in which the antenna impedance must be estimated indirectly, e.g., using the relative strength of the analog signal returned by a prior art tag 88 in response to interrogation by the reader 92, our method employs the on-chip re-tuning capability of our tag 88 to return a digital value which more directly indicates the effective antenna impedance. Using a reference table having a sufficiently fine resolution, it is possible to detect even modest changes in the relevant environmental conditions. It will be readily realized by practitioners in this art that, in general applications, environment conditions typically do not change in an ideal manner, and, more typically, changes in one condition are typically accompanied by changes in at least one other condition. Thus, antenna design will be important depending on the application of interest.

As noted in our Parent Provisional Two, one possible approach would be to mount the antenna 12 on a substrate that tends to amplify the environmental condition of interest, e.g., temperature.

Shown in FIG. 13 is an RF sensing system 104 constructed in accordance with one embodiment of our invention, and specially adapted to facilitate sensing of one or more environmental conditions in a selected region surrounding the system 104. In general, the system 104 comprises: an RF transceiver 106; a di-pole antenna 108 comprising a pole 108 a and an anti-pole 108 b; and a tail 110 of effective length T, comprising respective transmission line pole 110 a and transmission line anti-pole 110 b, each of length T/2. In accordance with our invention, the differential transmission line elements 110 a-110 b are symmetrically coupled to respective poles 108 a-108 b at a distance d from the axis of symmetry of the antenna 108 (illustrated as a dotted line extending generally vertically from the transceiver 106). In general, d determines the strength of the interaction between the transmission line 110 and the antenna 108, e.g., increasing d tends to strengthen the interaction. In the equivalent circuit shown in FIG. 13b , the voltage differential between the complementary voltage sources 108 a and 108 b tends to increase as d is increased, and to decrease as d is decreased. Preferably d is optimized for a given application. However, it will be recognized that the sensitivity of the antenna may be degraded as a function of d if a load, either resistive or capacitive, is imposed on the tail 110.

In operation, the tail 110 uses the transmission line poles 110 a-110 b to move the impedance at the tip of the tail 110 to the antenna 108, thus directly affecting the impedance of the antenna 108. Preferably, the transceiver 106 incorporates our tuning circuit 16 so as to detect any resulting change in antenna impedance and to quantize that change for recovery, e.g., using the method we have described above with reference to FIG. 12.

By way of example, we have illustrated in FIG. 14 one possible embodiment of the system 104 in which the antenna poles 108 a-108 b are instantiated as a patch antenna (illustrated in light grey), with the antenna pole 108 a connected to one output of transceiver 106, and the other output of transceiver 106 connected to the antenna anti-pole 108 b. A ground plane 112 a (illustrated in a darker shade of grey than the patch antenna 108) is disposed substantially parallel to both the antenna poles 108 a-108 b and a ground plane 112 b disposed substantially parallel to the transmission line poles 110 a-110 b. As is known, the ground planes 112 are separated from the poles by a dielectric substrate (not shown), e.g., conventional flex material or the like. If the dielectric layer between the antenna poles 108 and ground plane 112 a is of a different thickness than the layer between the transmission line poles 110 and the ground plane 112 b, the ground plane 112 b may be disconnected from the ground plane 112 a and allowed to float. In general, this embodiment operates on the same principles as described above with reference to FIG. 13.

Shown in FIG. 15 is an antenna 114 constructed in accordance with one other embodiment of our invention, and specially adapted for use in the sensing system 104 to facilitate sensing the presence of fluids; and, in particular, to the depth of such fluids. In the illustrated embodiment, antenna 114 comprises a head portion 116 and a tail portion 118. In general, the head 116 is adapted to receive RF signals and to transmit responses using conventional backscatter techniques; whereas the tail portion 118 functions as a transmission line. During normal operation, the tail 118 acts to move and transform the impedance at the tip of the tail to the head 116. Accordingly, any change in the tip impedance due to the presence of fluid will automatically induce a concomitant change in the impedance of the head antenna 116. As has been explained above, our tuning circuit 16 will detect that change and re-adjust itself so as to maintain a reactive impedance match. As has been noted above, any such adjustment is reflected in changes in the digital value stored in shift register 90 (FIG. 11).

Shown in FIG. 16 is one possible flow for a sensing system 104 using the antenna 114. As has been explained above with reference to FIG. 12, the sensor is first calibrated (step 120) to detect the presence of varying levels of a particular substance. For the purposes of this discussion, we mean the term substance to mean any physical material, whether liquid, particulate or solid, that is: detectable by the sensor; and to which the sensor demonstrably responds. By detectable, we mean that, with respect to the resonant frequency of the antenna 114 in the absence of the substance, the presence of the substance in at least some non-trivial amount results in a shift in the resonant frequency of the antenna 114, thereby resulting in a concomitant adjustment in the value stored in the shift register 90; and by demonstrably responds we mean that the value stored in the shift register 90 varies as a function of the level the substance relative to the tip of the tail 118 of the antenna 114. Once calibrated, the sensor can be installed in a structure (step 122), wherein the structure can be open, closed or any condition in between. The structure can then be exposed to the substance (step 124), wherein the means of exposure can be any form appropriate for both the structure and the substance, e.g., sprayed in aerosol, foam or dust form, immersed in whole or in part in a liquid, or other known forms. Following a period of time deemed appropriate for the form of exposure, the sensor is interrogated (step 126) and the then-current value stored in the shift register 90 retrieved. By correlating this value with the table of calibration data gathered in step 120, the presence or absence of the substance can be detected (step 128).

In one embodiment, the table of calibration data can be stored in the sensor and selectively provided to the reader during interrogation to retrieve the current value. Alternatively, the table can be stored in, e.g., the reader and selectively accessed once the current value has been retrieved. As will be clear, other embodiments are possible, including storing the table in a separate computing facility adapted to selectively perform the detection lookup when a new current value has been retrieved.

Assume by way of example, an automobile assembly line that includes as an essential step the exposure, at least in part, of a partially-assembled automobile chassis to strong streams of a fluid, e.g., water, so as to determine the fluid-tightness of the chassis. Given the complexity of a modern automobile, it is not cost effective to manually ascertain the intrusion of the fluid at even a relatively small number of possible points of leakage. However, using our sensors and sensing system 104, we submit that it is now possible to install relatively large numbers of independently operable sensors during the assembly process, even in highly inaccessible locations such as largely-enclosed wiring channels and the like. In the course of such installations, the unique identity codes assigned to each installed sensor is recorded together with pertinent installation location details. After extraction from the immersion tank, the chassis can be moved along a conventional conveyor path past an RFID reader sited in a position selected to facilitate effective querying of all of the installed sensors. In one embodiment, the reader may be placed above the moving chassis so as to “look down” through the opening provided for the front windshield (which may or may not be installed) into the interior portion of the chassis; from such a position even those sensors installed in the “nooks and crannies” in the trunk cavity should be readable. By correlating the code read from each sensor with the previously constructed, corresponding table, it is now possible to detect the presence (or absence) of the substance at the respective location of that sensor; indeed, if the sensor is sufficiently sensitive to the substance, it may be possible to estimate the severity of the leakage in the vicinity of each sensor.

Shown in FIG. 17 is an antenna 130 constructed in accordance with one other embodiment of our invention, and specially adapted for use in the sensing system 104 to facilitate sensing the presence of fluids; and, in particular, to the depth of such fluids. As illustrated in FIG. 17a , the top layer of antenna 132 comprises: a patch antenna portion 134; an antenna ground plane 136; a tail portion 138; and a die attach area 140. As noted in FIG. 17a , the tail portion 138 of antenna 130 comprises a pair of generally parallel transmission lines 142, each substantially the same in length. As illustrated in FIG. 17b , the bottom layer of antenna 130 comprises a ground plane 136 for the transmission lines 142. During a typical assembly process, the illustrated shapes are formed in the top and bottom layers of a continuous roll of copper-clad flex circuit material, and each antenna 130 cut from the roll using a rolling cutter assembly. An RFID tag device (incorporating our tuning circuit 16) is then attached to the die attach area 140, and the antenna 130 is folded along fold lines 1 and 2 generally around a suitable core material such as PET or either open-cell or closed-cell foam.

In general, the patch antenna portion 134 is adapted to receive RF signals and to transmit responses using conventional backscatter techniques. During normal operation, the transmission lines 142 comprising the tail 138 act to move and transform the impedance at the tip of the tail 138 to the patch antenna 134. Accordingly, any change in the tip impedance due to the presence of fluid will automatically induce a concomitant change in the impedance of the head antenna 1. As has been explained above, our tuning circuit 16 will detect that change and re-adjust itself so as to maintain a reactive impedance match. As has been noted above, any such adjustment is reflected in changes in the digital value stored in shift register 90 (FIG. 11).

FIG. 18 is a logic diagram of an example of a method of adjusting impedance of a radio frequency identification (RFID) tag in accordance with a power level threshold. The method begins at step 146 an antenna of the RFID tag receives a radio frequency (RF) signal from an RFID reader. The RF signal has a carrier frequency of a plurality of carrier frequencies. The plurality of carrier frequencies spans a broad frequency band.

The method continues with step 148 where a tuning circuit of the RFID tag determines a received power level of the RF signal at the carrier frequency. The tuning circuit may include a processing module. The RFID tag may further include a regulator operable to convert the received RF signal into a power supply voltage that powers the tuning circuit

The method continues with step 150 where the tuning circuit determines whether the received power level compares favorably to a power level threshold. The threshold power level corresponds to a power level that occurs when the carrier frequency is substantially equal to a resonant frequency of at least one of the antenna and a tank circuit of the RFID tag. The tank circuit is coupled to the antenna, and the input impedance of the RFID tag is based on one or more of impedance of the antenna and impedance of the tank circuit. The antenna is further operable to receive an input command from an RFID reader. The tuning circuit may determine a required power level to complete the input command and set the required power level as the power level threshold.

The method continues with step 152 where, when the received power level compares unfavorably to the power level threshold, the tuning circuit adjusts the input impedance of the RFID tag by adjusting the tank circuit of the RFID tag until the received power level compares favorably to the power level threshold. The tank circuit may include an inductor and a variable capacitor and the tuning circuit is operable to adjust the variable capacitor. As another example, the tank circuit may include a capacitor and a variable inductor and the tuning circuit is operable to adjust the variable inductor.

The tuning circuit may further include a reference circuit operable to generate a power reference of the received RF signal, a comparison circuit operable to compare a current power reference of a current power level of the received RF signal with the power level threshold, and a control signal circuit operable to generate a control signal based on the comparing of the current power reference with the power level threshold.

Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of our invention. Therefore, we intend that our invention encompass all such variations and modifications as fall within the scope of the appended claims.

It is noted that terminologies as may be used herein such as bit stream, stream, signal sequence, etc. (or their equivalents) have been used interchangeably to describe digital information whose content corresponds to any of a number of desired types (e.g., data, video, speech, text, graphics, audio, etc. any of which may generally be referred to as ‘data’).

As may be used herein, the terms “substantially” and “approximately” provides an industry-accepted tolerance for its corresponding term and/or relativity between items. For some industries, an industry-accepted tolerance is less than one percent and, for other industries, the industry-accepted tolerance is 10 percent or more. Other examples of industry-accepted tolerance range from less than one percent to fifty percent. Industry-accepted tolerances correspond to, but are not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, thermal noise, dimensions, signaling errors, dropped packets, temperatures, pressures, material compositions, and/or performance metrics. Within an industry, tolerance variances of accepted tolerances may be more or less than a percentage level (e.g., dimension tolerance of less than +/−1%). Some relativity between items may range from a difference of less than a percentage level to a few percent. Other relativity between items may range from a difference of a few percent to magnitude of differences.

As may also be used herein, the term(s) “configured to”, “operably coupled to”, “coupled to”, and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for an example of indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”.

As may even further be used herein, the term “configured to”, “operable to”, “coupled to”, or “operably coupled to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform, when activated, one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term “associated with”, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item.

As may be used herein, the term “compares favorably”, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1. As may be used herein, the term “compares unfavorably”, indicates that a comparison between two or more items, signals, etc., fails to provide the desired relationship.

As may be used herein, one or more claims may include, in a specific form of this generic form, the phrase “at least one of a, b, and c” or of this generic form “at least one of a, b, or c”, with more or less elements than “a”, “b”, and “c”. In either phrasing, the phrases are to be interpreted identically. In particular, “at least one of a, b, and c” is equivalent to “at least one of a, b, or c” and shall mean a, b, and/or c. As an example, it means: “a” only, “b” only, “c” only, “a” and “b”, “a” and “c”, “b” and “c”, and/or “a”, “b”, and “c”.

As may also be used herein, the terms “processing module”, “processing circuit”, “processor”, “processing circuitry”, and/or “processing unit” may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processing module, module, processing circuit, processing circuitry, and/or processing unit may be, or further include, memory and/or an integrated memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of another processing module, module, processing circuit, processing circuitry, and/or processing unit. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, module, processing circuit, processing circuitry, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via a wired and/or wireless bus structure) or may be distributedly located (e.g., cloud computing via indirect coupling via a local area network and/or a wide area network). Further note that if the processing module, module, processing circuit, processing circuitry and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory element storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Still further note that, the memory element may store, and the processing module, module, processing circuit, processing circuitry and/or processing unit executes, hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the Figures. Such a memory device or memory element can be included in an article of manufacture.

One or more embodiments have been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claims. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality.

To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claims. One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.

In addition, a flow diagram may include a “start” and/or “continue” indication. The “start” and “continue” indications reflect that the steps presented can optionally be incorporated in or otherwise used in conjunction with one or more other routines. In addition, a flow diagram may include an “end” and/or “continue” indication. The “end” and/or “continue” indications reflect that the steps presented can end as described and shown or optionally be incorporated in or otherwise used in conjunction with one or more other routines. In this context, “start” indicates the beginning of the first step presented and may be preceded by other activities not specifically shown. Further, the “continue” indication reflects that the steps presented may be performed multiple times and/or may be succeeded by other activities not specifically shown. Further, while a flow diagram indicates a particular ordering of steps, other orderings are likewise possible provided that the principles of causality are maintained.

The one or more embodiments are used herein to illustrate one or more aspects, one or more features, one or more concepts, and/or one or more examples. A physical embodiment of an apparatus, an article of manufacture, a machine, and/or of a process may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the embodiments discussed herein. Further, from figure to figure, the embodiments may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers and, as such, the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different ones.

While the transistors in the above described figure(s) is/are shown as field effect transistors (FETs), as one of ordinary skill in the art will appreciate, the transistors may be implemented using any type of transistor structure including, but not limited to, bipolar, metal oxide semiconductor field effect transistors (MOSFET), N-well transistors, P-well transistors, enhancement mode, depletion mode, and zero voltage threshold (VT) transistors.

Unless specifically stated to the contra, signals to, from, and/or between elements in a figure of any of the figures presented herein may be analog or digital, continuous time or discrete time, and single-ended or differential. For instance, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. While one or more particular architectures are described herein, other architectures can likewise be implemented that use one or more data buses not expressly shown, direct connectivity between elements, and/or indirect coupling between other elements as recognized by one of average skill in the art.

The term “module” is used in the description of one or more of the embodiments. A module implements one or more functions via a device such as a processor or other processing device or other hardware that may include or operate in association with a memory that stores operational instructions. A module may operate independently and/or in conjunction with software and/or firmware. As also used herein, a module may contain one or more sub-modules, each of which may be one or more modules.

As may further be used herein, a computer readable memory includes one or more memory elements. A memory element may be a separate memory device, multiple memory devices, or a set of memory locations within a memory device. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. The memory device may be in a form a solid-state memory, a hard drive memory, cloud memory, thumb drive, server memory, computing device memory, and/or other physical medium for storing digital information.

While particular combinations of various functions and features of the one or more embodiments have been expressly described herein, other combinations of these features and functions are likewise possible. The present disclosure is not limited by the particular examples disclosed herein and expressly incorporates these other combinations. 

What is claimed is:
 1. A radio frequency identification (RFID) tag comprises: an antenna operable to receive a radio frequency (RF) signal, wherein the RF signal has a carrier frequency of a plurality of carrier frequencies, wherein the plurality of carrier frequencies spans a broad frequency band; a tank circuit coupled to the antenna, wherein an input impedance of the RFID tag is based on one or more of impedance of the antenna and impedance of the tank circuit; and a tuning circuit operable to: determine a received power level of the RF signal at the carrier frequency; determine whether the received power level compares favorably to a power level threshold; and when the received power level compares unfavorably to the power level threshold, adjust the input impedance of the RFID tag by adjusting the tank circuit until the received power level compares favorably to the power level threshold.
 2. The RFID tag of claim 1, wherein the threshold power level corresponds to a power level that occurs when the carrier frequency is substantially equal to a resonant frequency of at least one of the antenna and the tank circuit.
 3. The RFID tag of claim 1, wherein the tuning circuit includes a processing module.
 4. The RFID tag of claim 1 further comprises: the antenna is further operable to receive an input command from an RFID reader; and the tuning circuit is further operable to: determine a required power level to complete the input command; and set the required power level as the power level threshold.
 5. The RFID tag of claim 1, wherein the tank circuit comprises: an inductor; and a variable capacitor, wherein the tuning circuit is operable to adjust the variable capacitor.
 6. The RFID tag of claim 1, wherein the tank circuit comprises: a capacitor; and a variable inductor, wherein the tuning circuit is operable to adjust the variable inductor.
 7. The RFID tag of claim 1 further comprises: a regulator operable to convert the received RF signal into a power supply voltage that powers the tuning circuit.
 8. The RFID tag of claim 1, wherein the tuning circuit comprises: a reference circuit operable to generate a power reference of the received RF signal; a comparison circuit operable to compare a current power reference of a current power level of the received RF signal with the power level threshold; and control signal circuit operable to generate a control signal based on the comparing of the current power reference with the power level threshold.
 9. A method for execution by a radio frequency identification (RFID) tag, the method comprises: receiving, by an antenna of the RFID tag, a radio frequency (RF) signal from an RFID reader, wherein the RF signal has a carrier frequency of a plurality of carrier frequencies, wherein the plurality of carrier frequencies spans a broad frequency band; determining, by a tuning circuit of the RFID tag, a received power level of the RF signal at the carrier frequency; determining, by the tuning circuit, whether the received power level compares favorably to a power level threshold; and when the received power level compares unfavorably to the power level threshold, adjusting, by the tuning circuit, the input impedance of the RFID tag by adjusting a tank circuit of the RFID tag until the received power level compares favorably to the power level threshold, wherein the tank circuit is coupled to the antenna, and wherein the input impedance of the RFID tag is based on one or more of impedance of the antenna and impedance of the tank circuit.
 10. The method of claim 9, wherein the threshold power level corresponds to a power level that occurs when the carrier frequency is substantially equal to a resonant frequency of at least one of the antenna and the tank circuit.
 11. The method of claim 9, wherein the tuning circuit includes a processing module.
 12. The method of claim 9 further comprises: receiving, by the antenna, an input command from the RFID reader; determining, by the tuning circuit, a required power level to complete the input command; and setting, by the tuning circuit, the required power level as the power level threshold. 